Solid State Measurements


110 Technology Drive • Pittsburgh, PA 15275 • USA
phone: 412.787.0620 • fax: 412.787.0630 email: info@ssm-inc.com www.ssm-inc.com

OVERCOMING THE ELECTRICAL BARRIER TO
DEVELOPING THE NEXT GENERATION OF CHIPS

By Charles Thomas, President and Chief Executive Officer,
Solid State Measurements, Inc.

The Holy Grail of electrical testing, or any kind of semiconductor testing for that matter, has been to develop technology to test product wafers nondestructively on the production line at production speed.

It has been more than 25 years since Gordon Moore first postulated his law that suggested the price of computing power would be cut in half every 18 months. The semiconductor fabrication industry is still attempting to drive down the cost of computing through miniaturization. But as the industry develops a new generation of semiconductors, the process of creating smaller circuits on larger wafers is beginning to collide with the laws of physics. Moore himself admitted in 1997 that the finite size of atoms would soon make his law obsolete, barring a radical shift in microprocessor technology.

Manufacturing and testing methods that worked well in the past are no longer adequate because of a convergence of technical challenges and marketplace demands:

These new demands have fueled a rapid development of new electrical testing technology over the past decade. Now, a new nondestructive probe technology enables semiconductor manufacturers to conduct electrical testing nondestructively on production wafers at production speeds. The cost savings can be enormous, and the accuracy and flexibility of the equipment facilitates continued miniaturization.

There are five electrical measurements that need to be performed in advanced semiconductor fabrication:

  1. The voltage at which the transistors switch
  2. The purity of the interface between the silicon dioxide and the silicon layers
  3. The transistor current, controlled in large part by gate oxide thickness
  4. The level of metallic and other contaminants
  5. The distribution of dopants within diffused and implanted layers (Dopants are metals such as boron added in trace amounts to the pure silicon to alter its conductive properties for use in transistors and diodes.)

For 30 years, all electrical testing probes for semiconductors were destructive to the wafer. To make electrical measurements, older probes used MOS technology, which required that monitor wafers, unpatterned wafers dedicated to process control, be pulled from the line and put through a time-consuming process in which special test pads were deposited on the wafer. The pads created a conductive metal-oxide silicon, or MOS, structure that could be tested for electrical characteristics. The process of depositing the MOS structure could take from 6 hours to 2 days, during which time production ran without a clue as to whether the wafers were good or bad.

Once the MOS structure was created, electrical measurements could be made. The tests were quite accurate, but the process was slow and very expensive. Remember, in those days, while electrical characteristics were important, they were not as critical as today, simply because circuit features were larger.

Mercury-based probes, first introduced in 1990, were a great advance over destructive testing, just as Windows 3.1 was a great advance over DOS. Mercury-based technology used mercury instead of poly-silicon pads as the metal-oxide-silicon structure. The industry could test wafers in less than 30 seconds for most measurements. And because the probe did not physically damage the wafer, it had the potential to cut material costs. But technicians disliked handling the mercury, and still had to test a monitor wafer, not a production wafer, because of the relatively large area needed for the mercury contact.

Soon after the mercury probe was introduced, several companies introduced the corona probe. Corona probes use several elaborate technologies to put a corona charge on the surface of the monitor wafer; in this context, a corona is an ionic electrical field produced at the surface of the wafer. The probes then perform indirect electrical measurements on the monitor wafer. While not requiring contact with the wafer, the process is still relatively slow, taking from 5-15 minutes to measure each wafer. The tests still require a large measurement area. Each piece of test equipment is relatively expensive, substantially driving up testing costs.

That brings us to the newest advancement in electrical testing, nondestructive probe technology. The probe makes nondestructive contact with the silicon oxide surface and is small enough to work in scribe lines, or streets, which are the spaces between each chip die on the wafer. Because of patented, low inertia, non-scrubbing probes, no particles are generated in the testing process, so no damage is inflicted on any wafer.

For example, Solid State Measurements is marketing a series of FastGate™ Metrology Systems, which use an elastic probe made from materials compatible with semiconductor processing as a non-damaging contact to form the MOS diode. This temporary gate can be formed very rapidly (in seconds) with no damage or contamination to the underlying wafer. Because it has a diameter of only 30 microns, it can be formed within the scribe lines of production wafers.

The SSM FastGate™ Systems use well-understood and documented high-frequency capacitance-voltage (C-V) and current-voltage (I-V) techniques to conduct single-site measurements and maps on production or monitor wafers of up to 300-mm diameter. SSM’s proprietary analysis software contains a number of new data correction algorithms that permit highly precise electrical measurements to be taken. Tests are performed at production speed, and the tested wafers can continue to be processed after the electrical tests.

Nondestructive probe technology provides every benefit that the industry has been demanding for years in electrical testing of semiconductors:

    1. Equipment costs: One piece of equipment with a few probes can perform all the required electrical tests.
    2. Material costs: Currently, a significant portion of the production line capacity may be lost to monitor wafers. Because most fabricators typically need an 85 % yield just to break even, the savings resulting from testing production wafers drop right to the bottom line.
    3. Process time costs. Fast online electrical measurements close the process loop immediately and minimize scrap

The semiconductor fabrication process is amazingly complex, consisting of more than 250 production steps requiring the tightest of tolerances known to man, carried out in large fabrication facilities which run at full capacity, 24 hours per day, 7 days per week. Developing a way to test production wafers at production speeds represents a major step in the rapid development of the next generation of semiconductors.

Charles Thomas is President and Chief Executive Officer of Solid State Measurements, Inc., which designs and manufactures electrical testing equipment used in a variety of semiconductor applications.

The Evolution of Electrical Testing Equipment
for Semiconductor Fabrication

 

Challenge: Form a metal-oxide-semiconductor (MOS) diode that can be tested for electrical characteristics.

Technology How it works Drawbacks Test time per wafer Test area Wafer type
MOS CV system

(Introduced: 1980)

MOS gate deposited on a monitor wafer
  • Slow
  • Expensive to form the gate
  • Uses monitor wafer
6 hours —

2 days

50-µm fabrica-ted gate Monitor
Hg probe CV system

(Introduced: 1990)

Mercury used as MOS gate
  • Large testing area
  • Uses monitor wafer
30-120 seconds 0.5-mm diameter Monitor
Corona MOS biasing

(Introduced: 1995)

Corona charge placed on surface of wafer used as MOS gate
  • Very expensive
  • Slow
  • Large test surface
5 —15 minutes 5-mm diameter or full wafer Monitor
SSM Elastic Probe IV and CV system

(Introduced: 2000)

Elastic probe serves as MOS gate without damaging wafer   30-120 seconds 30-µm diameter Product

What the SSM 600 Elastic Probe Tests:

SSM 600 Elastic Probe Benefits:

· Measures product wafers

· Nondestructive

· Fast

· High precision

· High accuracy

· Reduces equipment and material costs

· Tests dielectric integrity

· Ease of maintenance

Index of white papers and bylined articles